Integrated Circuits (ICs) like System-On-Chip (SOC) are extensively used in analog, digital, mixed signal and Radio Frequency (RF) applications. A SOC usually includes, among other things, a microprocessor core, external interfaces, timing sources, analog interfaces, and embedded memories. Various examples of embedded memories are RAMs, ROMs or EEPROMs, etc. Embedded memories are preferred over other memories, such as external memories, due to a number of advantages. For example, embedded memories have faster response time, reduced number of chips and reduced pin count, consume less power, and are more cost effective as compared to the external memories. Moreover, the usage of embedded memories with built-in column multiplexers provides additional flexibility in the physical design and layout of the SOC.
FIG. 1 illustrates a block diagram of embedded memory architecture 100 with a built-in 2:1 column multiplexer. The embedded memory architecture 100 includes an address pre-decoder 102, a row decoder 104, a column decoder 106, a memory array 108, a column multiplexer 110, a sense amplifier unit 112, a data buffer unit 114, and a data register unit 116. The column multiplexer 110 as shown in the figure is a 2:1 column multiplexer, which means that each physical row of the embedded memory is equivalent to two words. It should be appreciated by people skilled in the art that the size of the column multiplexer may be more than 2:1 based on the requirements of the embedded memory. Therefore, column multiplexing allows wider embedded memories for given physical dimensions. Over the years, due to reduction in the physical dimensions of the SOC, size of the embedded memories has shrunk while the bit density (number of bits stored per unit area) has increased. Due to the increased bit density, embedded memories become prone to manufacturing process faults, and more specifically to proximity-based faults (faults due to physical proximity of the bit cells). For embedded memory with built-in column multiplexers, the physical proximity could be word line-based proximity or bit line-based proximity.
FIG. 2 illustrates word line proximity and bit line proximity in a memory array 200. The memory array 200 represents a row and column arrangement of bit cells, such as a bit cell 202. The memory array 200 includes two consecutive bit lines, such as bit lines 204a and 204b, and two consecutive word lines, such as word lines 206a and 206b. It should be realized by people skilled in the art that each bit cell, such as the bit cell 202, may be represented by the intersection of bit lines and word lines. Further, the memory array 200 includes a row address (X-address) space 208 and a column address (Y-address) space 210 representing the range of consecutive row and column addresses respectively. In case of bit line-based proximity, the consecutive bit cells differ in Y-address. For the word line-based proximity, the consecutive bit cells differ in X-address. BIST mechanism is generally used for testing the proximity-based faults, both-word line-based proximity faults and bit line-based proximity faults. In a typical BIST mechanism, a BIST controller is connected to the embedded memory. The BIST controller writes and reads the test pattern on different memory locations.
A single BIST controller is used to generate addresses corresponding to the memory cells contained in the various embedded memories. Further, the embedded memories have the same functional behavior but may have different structures. The difference in structure includes different number of physical rows, columns, different sizes of the column multiplexer, and so forth. The sequential testing of the various embedded memories using BIST may require considerable amount of time, primarily for address generation. Simultaneously testing the various embedded memories may reduce the testing time.
Various techniques exist in the art to simultaneously test multiple embedded memories having column multiplexers' of different sizes. One such technique is to generate a single address which is applicable for the memory with the largest column multiplexer, hereinafter referred to as primary memory. This address is appropriately transformed into addresses for other memories, hereinafter referred to as secondary memories. The transformation of the address generated for the primary memory to a valid secondary memory address is based upon the address generated for the primary memory, the ratio of the primary memory column multiplexer size to the secondary memory column multiplexer size, and the column multiplexer size of the secondary memory.
A limitation of the above mentioned technique is failure to test a range of memory locations of the secondary memories. This may happen in a scenario when the number of physical rows in the secondary memory is more than the number of physical rows in the primary memory. Further, there may be a few memory locations in the secondary memory which are tested more than once, leading to duplication of effort and elongation in testing time. Moreover, the generated address sequence of addresses may be incorrect with respect to the address sequence as required by the proximity-based BIST algorithm.
Another technique for simultaneous testing of the multiple embedded memories is to generate addresses individually for each memory. This technique suffers from the limitation of requiring a larger chip area for storing one address register for each memory. Typically, for a large number of embedded memories on the SOC, the increase in chip area is significant, and leads to an increment in the manufacturing cost of the product.
In view of the aforesaid challenges, there exists a need for an optimized method and a system to generate addresses for memories and simultaneously test the memories using a single Built-in Self Testing (BIST) controller. The method should simultaneously test different memories having different sizes of the column multiplexer preferably with all the address locations being tested only once. Thus, a lot of time and effort is saved. Further, the method should preferably not result in a significant increase in the chip area requirement, and should preferably maintain the correct address sequence of the memories as generally required by a proximity-based BIST algorithm.